Sys-ASIC Designs is a training and consulting company in ASIC/SoC/FPGA development. The main areas are in system-level verification, front-end design and verification methodology.
Management Profile:
Mr. C.K. Chang has 30 years of experience in chip development in Asia and USA.
At Sys-ASIC Designs, he provides training and services with a focus on system-level verification, front-end design and verification methodology, including use of SystemVerilog, SystemVerilog Assertions (SVA) and Universal Verification Methodology (UVM). Some of the clients include Nations Technologies, HP Enterprise, A*Star, Silicon Labs, Infineon, and others.
Prior to this, he was a technical staff at AMCC/JNI Corporation (Singapore) and participated in architecture, design and verification of 10Gbit Fibre Channel host adapter ASICs. Previous to that, he was a Senior Staff Engineer at Silicon Systems (Singapore), a subsidiary of Texas Instruments Inc, and was involved in the design of Firewire storage integrated circuits.
Prior to returning to Asia, he worked in Silicon Valley, California, USA at ESS Technology, 3DO Company and Sun Microsystems in architecture, design and verification of various ASIC development projects.
Mr. Chang has experience and knowledge in industry standard protocols including PCIe, SATA, Fibre Channel, USB, IEEE 1394 (Firewire), ARM/AMBA/AHB/APB, I2C, SPI, UFS, eMMC and JTAG 1149.